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features ? 1m x 8 or 512k x 16 organization ? +12.5v programming voltage ? fast access time: 100/120/150/200 ns ? totally static operation ? completely ttl compatible ? operating current: 60ma ? standby current: 100ua ? package type: - 42 pin plastic dip - 44 pin sop rev. 2.4, nov. 19, 2002 p/n: pm0261 1 general description the mx27c8100 is a 5v only, 8m-bit, one time program- mable read only memory. it is organized as 1m x 8 or 512k x 16, operates from a single + 5 volt supply, has a static standby mode, and features fast single address location programming. all programming signals are ttl levels, requiring a single pulse. for programming outside from the system, existing eprom programmers may be used. the mx27c8100 supports a intelligent fast pro- gramming algorithm which can result in programming time of less than two minutes. this one time programmable read only memory is packaged in industry standard 42 pin dual-in-line plastic package and 44 pin sop packages. pin configurations pdip block diagram sop mx27c8100 8m-bit [1m x8/512k x16] cmos otp rom mx27c8100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce gnd oe q0 q8 q1 q9 q2 q10 q3 q11 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 nc a8 a9 a10 a11 a12 a13 a14 a15 a16 byte/vpp gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce gnd oe q0 q8 q1 q9 q2 q10 q3 q11 nc nc a8 a9 a10 a11 a12 a13 a14 a15 a16 byte/vpp gnd q15/a1 q7 q14 q6 q13 q5 q12 q4 vcc mx27c8100 control logic output buffers q0~q14 q15/a-1 ce oe byte/vpp a0~a18 address inputs y-decoder x-decoder y-select 8m bit cell maxtrix vcc gnd . . . . . . . . . . . . . . . .
2 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 symbol pin name a0~a18 address input q0~q14 data input/output ce chip enable input oe output enable input byte/vpp word/byte selection/program supply voltage q15/a-1 q15(word mode)/lsb addr. (byte mode) vcc power supply pin (+5v) gnd ground pin pin description word mode(byte = vcc) ce oe q15/a-1 mode q0-q14 supply current h x high z non selected high z standby(icc2) l h high z non selected high z operating(icc1) l l dout selected dout operating(icc1) note : x = h or l truth table of byte function byte mode(byte = gnd) ce oe q15/a-1 mode q0-q7 supply current h x x non selected high z standby(icc2) l h x non selected high z operating(icc1) l l a-1 input selected dout operating(icc1)
3 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 functional description the programming of the mx27c8100 when the mx27c8100 is delivered, the chip has all 8m bits in the "one" or high state. "zeros" are loaded into the mx27c8100 through the procedure of programming. for programming, the data to be programmed is applied with 16 bits in parallel to the data pins. vcc must be applied simultaneously or before vpp, and removed simultaneously or after vpp. when programming an mxic one time programmable read only memory, a 0.1uf capacitor is required across vpp and ground to suppress spurious voltage transients which may damage the device. fast programming the device is set up in the fast programming mode when the programming voltage vpp = 12.75v is applied, with vcc = 6.25 v and oe = vih (algorithm is shown in figure 1). the programming is achieved by applying a single ttl low level 50us pulse to the ce input after addresses and data line are stable. if the data is not verified, an additional pulse is applied for a maximum of 25 pulses. this process is repeated while sequencing through each address of the device. when the programming mode is completed, the data in all address is verified at vcc = vpp = 5v 10%. program inhibit mode programming of multiple mx27c8100's in parallel with different data is also easily accomplished by using the program inhibit mode. except for ce and oe, all like inputs of the parallel mx27c8100 may be common. a ttl low-level program pulse applied to an mx27c8100 ce input with vpp = 12.5 0.5 v will program the mx27c8100. a high-level ce input inhibits the other mx27c8100 from being programmed. program verify mode verification should be performed on the programmed bits to determine that they were correctly programmed. the verification should be performed with oe at vil, ce at vih, and vpp at its programming voltage. auto identify mode the auto identify mode allows the reading out of a binary code from an one time programmable read only memory that will identify its manufacturer and device type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when programming the mx27c8100. to activate this mode, the programming equipment must force 12.0 0.5 v on address line a9 of the device. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from vil to vih. all other address lines must be held at vil during auto identify mode. byte 0 ( a0 = vil) represents the manufacturer code, and byte 1 (a0 = vih), the device identifier code. for the mx27c8100, these two identifier bytes are given in the mode select table. all identifiers for manufacturer and device codes will possess odd parity, with the msb (q15) defined as the parity bit. read mode the mx27c8100 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. chip enable (ce) is the power control and should be used for device selection. output enable (oe) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (tacc) is equal to the delay from ce to output (tce). data is available at the outputs toe after the falling edge of oe's, assuming that ce has been low and addresses have been stable for at least tacc - t oe. word-wide mode with byte/vpp at vcc 0.2v outputs q0-7 present data q0-7 and outputs q8-15 present data q8-15, after ce and oe are appropriately enabled.
4 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 mode select table byte/ mode ce oe a9 a0 q15/a-1 vpp(5) q8-14 q0-7 read (word) vil vil x x q15 out vcc q8-14 out q0-7 out read (upper byte) vil vil x x vih gnd high z q8-15 out read (lower byte) vil vil x x vil gnd high z q0-7 out output disable vil vih x x high z x high z high z standby vih x x x high z x high z high z program vil vih x x q15 in vpp q8-14 in q0-7 in program verify vih vil x x q15 out vpp q8-14 out q0-7 out program inhibit vih vih x x high z vpp high z high z manufacturer code(3) vil vil vh vil 0b vcc 00h c2h device code(3) vil vil vh vih 1b vcc 38h 16h notes: 1. vh = 12.0v 0.5v 2. x either vil or vih. 3. a1 - a8, a10 - a18 = vil (for auto select) 4. see dc programming characteristics for vpp voltages. 5. byte/vpp is intended for operation under dc voltage conditions only. 6. manufacture code = 00c2h device code = b816h it is recommended that ce be decoded and used as the primary device-selecting function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. system considerations during the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. at a minimum, a 0.1 uf ceramic capacitor (high frequency, low inherent inductance) should be used on each device between vcc and gnd to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on one time programmable read only memory arrays, a 4.7 uf bulk electrolytic capacitor should be used between vcc and gnd for each eight devices. the location of the capacitor should be close to where the power supply is connected to the array. byte-wide mode with byte/vpp at gnd 0.2v, outputs q8-15 are tri- stated. if q15/a-1 = vih, outputs q0-7 present data bits q8-15. if q15/a-1 = vil, outputs q0-7 present data bits q0-7. standby mode the mx27c8100 has a cmos standby mode which reduces the maximum vcc current to 100 ua. it is placed in cmos standby when ce is at vcc 0.3 v. the mx27c8100 also has a ttl-standby mode which reduces the maximum vcc current to 1.5 ma. it is placed in ttl-standby when ce is at vih. when in standby mode, the outputs are in a high-impedance state, independent of the oe input. two-line output control function to accommodate multiple memory connections, a two- line control function is provided to allow for: 1. low memory power dissipation, 2. assurance that output bus contention will not occur.
5 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 start address = first location vcc = 6.25v vpp = 12.75v x = 0 program one 50us pulse increment x x = 25? verify byte last address vcc = vpp = 5.25v device passed verify all bytes ? device failed increment address interactive section verify section fail pass yes pass no yes no fail figure 1. fast programming flow chart fail ?
6 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 switching test circuits switching test waveforms device under test diodes = in3064 or equivalent cl = 100 pf including jig capacitance 6.2k ohm 1.8k ohm +5v cl 2.0v 0.8v test points input 2.0v 0.8v output ac testing: ac driving levels are 2.4v/0.4v. input pulse rise and fall times are < 10ns. ac driving levels
7 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 notice: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are subject to change. absolute maximum ratings rating value ambient operating temperature 0 o c to 70 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to vcc + 0.5v vcc to ground potential -0.5v to 7.0v a9 & vpp -0.5v to 13.5v dc/ac operating conditions for read operation mx27c8100 -10 -12 -15 -20 operating temperature commercial 0 c to 70 c0 c to 70 c0 c to 70 c0 c to 70 c vcc power supply 5v 10% 5v 10% 5v 10% 5v 10% dc characteristics symbol parameter min. max. unit conditions voh output high voltage 2.4 v ioh = -0.4ma vol output low voltage 0.4 v iol = 2.1ma vih input high voltage 2.0 vcc + 0.5 v vil input low voltage -0.3 0.8 v ili input leakage current -10 10 ua vin = 0 to 5.5v ilo output leakage current -10 10 ua vout = 0 to 5.5v icc3 vcc power-down current 100 ua ce = vcc 0.3v icc2 vcc standby current 1.5 ma ce = vih icc1 vcc active current 60 ma ce = vil, f=5mhz, iout = 0ma ipp vpp supply current read 10 ua ce = oe = vil, vpp = 5.5v capacitance ta = 25 o c, f = 1.0 mhz (sampled only) symbol parameter typ. max. unit conditions cin input capacitance 8 12 pf vin = 0v cout output capacitance 8 12 pf vout = 0v cvpp vpp capacitance 18 25 pf vpp = 0v
8 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 ac characteristics 27c8100-10 27C8100-12 27c8100-15 27c8100-20 symbol parameter min. max. min. max. min. max. min. max. unit conditions tacc address to output delay 100 120 150 200 ns ce = oe = vil tce chip enable to output delay 100 120 150 200 ns oe = vil toe output enable to output delay 40 50 65 80 ns ce = vil tdf oe high to output float, 0 30 0 35 0 50 0 50 ns or ce high to output float0 toh output hold from address, 0 0 0 0 ns ce or oe which ever occurred first tbha byte access time 100 120 150 200 ns tohb byte output hold time 0 0 0 0 ns tbhz byte output delay time 70 70 70 70 ns tblz byte output set time 10 10 10 10 ns ac programming characteristics ta = 25 o c 5 o c symbol parameter min. typ. max. unit tas address setup time 2.0 us toes oe setup time 2.0 us tds data setup time 2.0 us tah address hold time 0 us tdh data hold time 2.0 us tdfp chip enable to output float delay 0 130 ns tvcs vcc setup time 2.0 us tvps byte/vpp setup time 2.0 us tpw ce initial program pulse width 50 us toe data valid from oe 150 ns dc programming characteristics ta = 25 o c 5 o c symbol parameter min. max. unit conditions voh output high voltage 2.4 v ioh = -0.40ma vol output low voltage 0.4 v iol = 2.1ma vih input high voltage 2.0 vcc + 0.5 v vil input low voltage -0.3 0.8 v ili input leakage current -10 10 ua vin = 0 to 5.5v vh a9 auto select voltage 11.5 12.5 v icc3 vcc supply current (program & verify) 50 ma ipp2 vpp supply current(program) 30 ma ce = vil, oe = vih vcc1 fast programming supply voltage 6.00 6.50 v vpp1 fast programming voltage 12.5 13.0 v
9 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 waveforms read cycle(word mode) read cycle(byte mode) address inputs data out oe ce data address valid data tdf tacc tce toe toh tacc toh tbha tblz tohb tbhz high-z valid data valid data high-z a-1 byte/vpp q0-q7 q15-q8 valid data
10 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 waveforms fast programming algorithm waveforms addresses ce oe data byte/vpp vcc vih vil vpp1 vcc vcc1 vcc vih vil vih vil data out valid data set valid address tas tvps tvcs toe tpw tds tdh toes tdfp tah verify program
11 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 plastic package part no. access time operating current standby current package (ns) max.(ma) max.(ua) mx27c8100pc-10 100 60 100 42 pin dip(rom pin out) mx27c8100pc-12 120 60 100 42 pin dip(rom pin out) mx27c8100pc-15 150 60 100 42 pin dip(rom pin out) mx27c8100pc-20 200 60 100 42 pin dip(rom pin out) mx27c8100mc-10 100 60 100 44 pin sop(rom pin out) mx27c8100mc-12 120 60 100 44 pin sop(rom pin out) mx27c8100mc-15 150 60 100 44 pin sop(rom pin out) mx27c8100mc-20 200 60 100 44 pin sop(rom pin out) ordering information
12 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 package information
13 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100
14 rev. 2.4, nov. 19, 2002 p/n: pm0261 mx27c8100 revision history revision no. description page date 2.0 1) eliminate interactive programming mode. 5/30/1997 2) programming pulse change from 100us to 50us 2.1 ipp : 100ua----> 10ua 8/8/1997 2.2 modify package information p12,13 jan/12/2000 2.3 modify package information: change title p12 no v/12/2001 modify package information: add coplanarity parameter p13 2.4 to modify package information p12,13 nov/19/2002
mx27c8100 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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